With the continuous development of integrated circuit (IC) manufacturing technology, the volume of the semiconductor devices has become smaller and smaller; and the parasitic capacitance among metals in ICs has become larger and larger. Thus, the resistance-capacitance (RC) delay issue has become more and more prominent. To solve the RC delay issue, a copper interconnect technique has been used to substitute the conventional aluminum interconnect technique because the resistivity of copper is smaller than the resistivity of aluminum.
In the ICs having the conventional aluminum interconnect structures, the metal lines are formed by etching the metal, followed by a dielectric material filling process, and a chemical mechanical polishing (CMP) process, etc. When the material of the metal lines is changed from aluminum to copper, because copper is very difficult to etch, an embedding process is a key step of the fabrication of the copper wires in the copper interconnect structure. The embedding process is also referred as a Damascene process.
Forming the metal interconnect structure by the embedding process does not need a copper etching process. FIGS. 1-4 illustrate semiconductor structures corresponding to certain stages of an existing embedding process for forming a metal interconnect structure. As shown FIG. 1, the embedding process includes providing a semiconductor substrate (not shown); forming a first metal layer 101 on the semiconductor substrate; forming a dielectric layer 102 covering the first metal layer 101; and forming contact through holes 103 and trenches 104 connecting with the contact through holes 103 in the dielectric layer 102. The cross-section of the contact through holes 103 and the trenches 104 presents a Damascene morphology.
As shown in FIG. 2, the method also includes forming a metal nitride barrier layer 105 on the side surfaces of the contact through holes 103 and the trenches 104. Further, as shown in FIG. 3, the method also includes forming a copper seed layer 106 on the metal nitride barrier layer 105. Further, as shown in FIG. 4, the method also includes forming a copper metal layer (not labeled) on the copper seed layer 106 by an electro-chemical plating (ECP) method. The metal copper layer is referred as a second metal layer 107 (the copper seed layer 106 is also claimed as a portion of the second metal layer 107). Then, the metal copper layer, the copper seed layer 106 and the metal nitride barrier layer 105 may be planarized by a chemical mechanical polishing (CMP) process, and a flat and smooth surface is obtained.
However, in the metal interconnect structures formed by the existing methods, the resistance of the metal nitride barrier layer is relatively high. The relatively high resistance increases the resistance between the first metal layer and the second metal layer. Accordingly, the RC delay issue becomes more severe. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.